This invention relates to digital data buffer circuits. Specifically, this invention is a method and apparatus for implementing a digital data buffer circuit, arranged as a first-in/first-out buffer, commonly known as a "FIFO". Digital data from a computer or other data source can be written into the "FIFO" at one rate while data can be read out of the "FIFO" at a later time by some other device at a possibly different rate in the same order in which the data was written in.
In digital data transfer applications, such as computer networks, digital data from a computer or other digital device is generated at some predetermined rate to be sent to another digital device with possibly a slower data transfer rate, i.e. a device incapable of receiving the data at the rate at which it is transmitted. A communications protocol is usually established between the machines whereby the receiving machine inhibits data transmission asynchronously when it is unable to reliably accept more data from the transmitter.
To reduce the time required to send data between two machines, buffer circuit or a "FIFO" can be connected between the sender and the receiver to smooth the transmission and reception of the digital data by allowing the sending machine to write or transmit data into the "FIFO" at its own rate without being interrupted by the receiving machine.
Where large blocks of digital data are to be exchanged between two computers at transmission rates above 100 megabytes per second, for example, a common problem in the transfer of the data is the inability of the receiving computer to accept data from the sending computer as fast as the sending computer can transmit the data. In real-time data acquisition systems, for example, where a data source outputs data at high rate, valuable information might be lost if the receiving device is unable to process the information in an orderly fashion, at the rate at which the data is generated. Where two computers are transferring large blocks of data between each other at high rates, the dead-time or wait-time that the sending computer must waste while waiting for the receiving system to "catchup" can be substantial because the computer receiving the data might have to repetitively interrupt data transmission from the sender.
Substantial time savings for the sending computer could be realized if there were a means provided to the sending computer to "dump" large blocks of data at high speed while simultaneously allowing the receiving computer to accept the data as it is able to, thereby freeing up the sending computer for other tasks much sooner than would otherwise be possible.
Existing buffer circuits or "FIFO" circuits typically use semiconductor memory devices to store data. Mechanical storage devices such as Winchester storage disks or magnetic tapes may also be used as temporary storage devices, however, currently available mechanical devices such as disks or magnetic tapes have read and write access times that are slow in comparison to most semiconductor devices. To accomodate high data transfer rates into and out of a "FIFO", i.e., over 100 megabytes per second, a semiconductor memory device must be used. Semiconductor memory devices that are currently available become more costly and consume more power as read/write access times decrease. In a "FIFO" architecture wherein large blocks of high-speed data words are to be buffered, i.e., more than 10.sup.6, 8-bit words, at speeds over 10.sup.8 bytes per second for example, the cost of currently available high-speed semiconductor memory devices capable of accepting data in the speed range of 100 megabytes per second becomes expensive; power consumption and the heat generated in a confined space becomes prohibitive.
Currently available metal oxide semiconductor dynamic random access memory devices, or MOS DRAMS as they are known in the art, despite being much more economical and consuming much less power, are currently unable to operate with read and write access times sufficiently short to transfer data at high rates, i.e. at or near 100 megabytes per second. It would be desirable to be able to store large amounts of data in a "FIFO" circuit using a variety of semiconductor memory devices, particularly MOS DRAMS whereby the cost per bit of storage is minimized and the electric power consumption minimized while "FIFO" capacity is maximized.
Accordingly, it is an object of this invention to provide a computer buffer circuit for storing and retrieving digital data.
Another object of this invention is to provide a buffer circuit capable of having a data transfer rate of at least 100 megabytes per second.
Another objective is to provide a buffer circuit with a storage capacity of at least 1 megabyte, minimizing the cost per bit of storage.
Another object is to provide a computer buffer circuit for storing and retrieving data on a Last-in/First-out basis.
Another object is to provide a computer buffer circuit for storing and retrieving data on a First-in/First-out basis.
Another object is to provide a computer buffer circuit for storing and retrieving data at rates up to 10.sup.8 bytes per second.
Additional objects, advantages and novelty of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention.